AppNote: Solstice-PV
Re-simulating ATE Pattern with Conditional Delayed Start
Often time a test pattern exercises one function of the device-under-test (DUT). If the pattern is re-used at different logic cone within a design, some device initialization needs to take place before the pattern can be applied.
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The requirements for re-simulating an ATE pattern accurately and generating useful validation reports are:
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1. The start of the pattern must wait until a certain condition (or a combined logic) has been met
2. The reporting of the tester cycle in the pattern must be offset by the actual start of the pattern
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This application note describes how Solstice-PV is used to meet the requirements.
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1. Delay Start Condition
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Consider a DUT with a signal called delayStart, which transitions from 0 to 1 at 10ns. At the 0 to 1 transition, you would like to start the application of the ATE pattern sourced from a TSSI waveforms database (WDB).
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Consider the original WDB with stimulus and response starting at 0ns:
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Here is the trigger signal:
Here is the desired simulation waveforms:
Here is a step-by-step instructions using the Solstice-PV's VerilogOut Tool:
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1. Insert into the Scenario canvas the operation Out->Verilog, and set it up to generate relative timing:
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2. Generate a testbench (cmd.v) and edit to replace INITIAL with a customized trigger statement:
3. Cycle Count Display
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Using TSSI's SignalEdit Tool to add a signal that will pulse high at the start of every cycle. The testbench will then count the edges and display the count when a pattern mismatch happens:
4. Add a cycleCounter to the testbench file:
5. Update the message displays to include the cycleCount:
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The actual test case can be downloaded here: [delayVoutStart.tgz]